Q. 공기업 사무직 비전공자 교육사항 채우기 위해 학은제라도 듣는게 나을까요?
어디라든 가고 싶습니다. 그런데 비전공자라 학교 교육 적는 칸에 적을 강의가 없습니다. 공란으로 두는건 많이 타격이 클까요? 지금이라도 학은제로 학교 교육사항 채워야하는지 고민이 됩니다.
Q. 쿼터스23.1 simulation오류
Waveform 만들려고 Simulation을 돌리면 이런 오류가 납니다…ㅠㅠ
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/23.1std/questa_fse/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off And_2_input -c And_2_input --vector_source="C:/Users/Administrator/Desktop/Waveform3.vwf" --testbench_file="C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun Mar 31 21:09:24 2024
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off And_2_input -c And_2_input --vector_source=C:/Users/Administrator/Desktop/Waveform3.vwf --testbench_file=C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (199013): HDL output file name "C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt" used with --testbench_file option contains a non-existent directory path
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 4712 megabytes
Error: Processing ended: Sun Mar 31 21:09:25 2024
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error.
Q. 안녕하세요 대기업 생산직 인적성 관련 질문드립니다.
어느 기업 서류를 합격하고 인적성을 보라는 메일이 왔는데 한날 한시에 치는 인적성이 아닌 정해진 기간동안에 개인적으로 치르는 시험입니다. 캠이나 마이크도 없이요. 이런식이면 부정행위가 일어날 가능성이 높지 않나요? 계산기를 쓴단던지 2명이서 같이 푼다던지 기업에서는 이떤 대처방안이 있길래 캠이나 마이크를 사용하지 않게 하고 시험을 치르게 하는지 궁금합니다.