대학생 고민 · 모든 회사 / 모든 직무

Q. (Verilog) 쿼터스23.1 버전 simulation 오류

Waveform 만들어 simulation하려는데 이렁 오류가 뜹니다.. 어떻게 해야 좋을까요ㅠㅠ

문으로 바로가기
네이버 메일메일 읽기
수정전달읽음삭제이동
뒤로 가기
메일 제목ff

2024년 3월 31일 (일) 오후 9:12
글자 크기 조정중요 메일
출발 언어영어도착 언어한국어번역하기
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/23.1std/questa_fse/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off And_2_input -c And_2_input --vector_source="C:/Users/Administrator/Desktop/Waveform3.vwf" --testbench_file="C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun Mar 31 21:09:24 2024
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off And_2_input -c And_2_input --vector_source=C:/Users/Administrator/Desktop/Waveform3.vwf --testbench_file=C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (199013): HDL output file name "C:/intelFPGA_lite/23.1std/simulation/qsim/../../Users/Administrator/Desktop/Waveform3.vwf.vt" used with --testbench_file option contains a non-existent directory path
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 4712 megabytes
Error: Processing ended: Sun Mar 31 21:09:25 2024
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01

Error.